The present invention is directed to wireless communications equipment and, more particularly, to an apparatus for RACH data reception and detection.
“Random access channel” (RACH) for telecommunications is defined in the context of the 3rd Generation Partnership Project (3GPP) standards, such as Long Term Evolution (LTE) and LTE Advanced. A physical RACH (PRACH) is used in uplink transmission from a User Equipment (UE) to a base station (NodeB or eNodeB). The PRACH can be used to access the network initially and when the UE loses its uplink synchronization. The PRACH can also be used to request radio resources, to carry control information and reference signals for time offset and adjusting the transmitted power, and to transmit small amounts of data. The PRACH has a role in contention resolution when UEs attempt to access the same NodeB by the same channel simultaneously, leading to collisions.
In LTE and LTE Advanced, PRACH are embedded in the same uplink (UL) transmissions as Physical Uplink Shared Channel (PUSCH) signals that transport Layer 1 UL data, Physical Uplink Control Channel (PUCCH) signals and Sounding Reference Symbols (SRS) that carry some control information. PRACH have specific sub-carrier spacing and specific symbol duration, different from PUSCH, PUCCH and SRS.
Reception and detection of the RACH signals is computationally intensive and involves processing a large quantity of data at high speeds. Conventional RACH reception and detection starts with decimation, which decimation filters and down samples the sampling rate to the sample rate of RACH, for example 1/12 for 20 MHz case. Decimation is typically performed in two steps, first a finite impulse response (FIR) filter operation that filters out the RACH neighbor frequencies for anti-aliasing, and second a down-sampling operation. The signal decimation is followed by Fast Fourier Transform (FFT) and removal of the guard interval. The signal after FFT is then multiplied by the conjugate of the RACH Zadoff-Chu (Z-C) reference sequence, resulting in a frequency domain representation of the fading channel path. An inverse FFT (iFFT) operation is performed on the multiplied signal to transform it from the frequency domain to the time domain. Then a delay profile of the time domain channel paths is computed and analyzed (searched for peaks) to make available the detected RACH signal.
Such intensive computation requires powerful digital signal processors (DSPs) and central processor unit (CPU) cores. However, it is desirable to increase the computational capacity of the processors, not only for more rapid RACH reception and detection, but also to release capacity for other functions.
General purpose DSPs and CPUs execute a sequence of stored instructions (software), and are capable of performing a wide variety of computational tasks. A hardware accelerator is able to speed up specialized tasks that require intensive repetitive calculation, such as FFT and iFFT. A major difference between hardware and software is concurrency of the hardware operation, allowing the hardware to be faster than software for certain specific tasks. In a conventional reception and detection system for LTE compliant PUSCH, RACH and SRS signals, a hardware accelerator is used for some tasks to improve the processing speed.
It would be advantageous to be able to more quickly process RACH reception and detection to achieve even more rapid processing performance.